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ICSSSTUA32S869B - 14-Bit Configurable Registered Buffer

Description

The ICSSSTUA32S869B is 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

Features

  • 14-bit 1:2 registered buffer with parity check functionality.
  • Supports SSTL_18 JEDEC specification on data inputs and outputs.
  • 50% more dynamic driver strength than standard SSTU32864.
  • Supports LVCMOS switching levels on C1 and RESET# inputs.
  • Low voltage operation VDD = 1.7V to 1.9V.
  • Available in 150 BGA package.
  • Green packages available Pin Configuration 1 A B C D E F G H J K L M N P R T U V W 2 3 4 5 6 7 8 9 10 11 150 Ball BGA.

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Datasheet Details

Part number ICSSSTUA32S869B
Manufacturer ICS
File Size 319.18 KB
Description 14-Bit Configurable Registered Buffer
Datasheet download datasheet ICSSSTUA32S869B Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.com Integrated Circuit Systems, Inc. ICSSSTUA32S869B Advance Information 14-Bit Configurable Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97U877 • Ideal for DDR2 400, 533 and 667 Product Features: • 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • 50% more dynamic driver strength than standard SSTU32864 • Supports LVCMOS switching levels on C1 and RESET# inputs • Low voltage operation VDD = 1.7V to 1.
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