Description
HY57V28420B(L)T 4Banks x 8M x 4bits Synchronous DRAM .
Features
* Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operationApplications
* which require large memory density and high bandwidth. HY57V28420B(L)T is organized as 4banks of 8,388,608x4. HY57V28420B(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The dataHY57V28420BLT Distributors
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