Description
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No.History 1.0 .
and is subject to change without notice.
Features
* Voltage: VDD, VDDQ 3.3V supply voltage
* 4096 Refresh cycles / 64ms
* All device pins are compatible with LVTTL interface
* Programmable Burst Length and Burst Type
* 54 Pin TSOPII (Lead or Lead Free Package)
- 1, 2, 4, 8 or full page for Sequential Burs
Applications
* which require wide data I/O and high bandwidth. HY57V281620E(L/S)T(P) series is organized as 4banks of 2,097,152 x 16.
HY57V281620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock i
