Datasheet Details
| Part number | 74F109 |
|---|---|
| Manufacturer | Fairchild (onsemi) |
| File Size | 79.72 KB |
| Description | Dual JK Positive Edge-Triggered Flip-Flop |
| Datasheet |
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The F109 consists of two high-speed, completely independent transition clocked JK flip-flops.
The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs.
| Part number | 74F109 |
|---|---|
| Manufacturer | Fairchild (onsemi) |
| File Size | 79.72 KB |
| Description | Dual JK Positive Edge-Triggered Flip-Flop |
| Datasheet |
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|
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| Part Number | Description | Manufacturer |
|---|---|---|
| 74F109 | Dual JK Positive Edge-Triggered Flip-Flop | National Semiconductor |
| 74F109 | Positive J-K positive edge-triggered flip-flops | NXP |
| 74F109 | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP | Texas Instruments |
| 74F10 | Triple 3-input NAND gate | NXP |
| 74F10 | Triple 3-Input NAND Gate | National Semiconductor |
| Part Number | Description |
|---|---|
| 74F10 | Triple 3-Input NAND Gate |
| 74F1056 | 8-Bit Schottky Barrier Diode Array |
| 74F1071 | 18-Bit Undershoot/Overshoot Clamp |
| 74F11 | Triple 3-Input AND Gate |
| 74F112 | Dual JK Negative Edge-Triggered Flip-Flop |
The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.