| Part number | CY7C1917BV18, CY7C1317BV18 |
|---|---|
| Manufacturer | Cypress Semiconductor |
| File Size | 447.88 KB |
| Description | 1.8V Synchronous Pipelined SRAM |
| Datasheet |
 CY7C1317BV18-CypressSemiconductor.pdf
|
| Note |
This datasheet PDF includes multiple part numbers: CY7C1917BV18, CY7C1317BV18. Please refer to the document for exact specifications by model. |
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) 300-MHz clock for high bandwidth 4-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 600MHz) @ 300 MHz Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches Echo clocks (CQ and CQ) simplify data cap
📁 CY7C1917BV18 Similar Datasheet
