CY7C1910BV18, CY7C1310BV18 - 1.8V Synchronous Pipelined SRAM

Cypress Semiconductor

Datasheet Details

Part number	CY7C1910BV18, CY7C1310BV18
Manufacturer	Cypress Semiconductor
File Size	390.16 KB
Description	1.8V Synchronous Pipelined SRAM
Datasheet	CY7C1310BV18-CypressSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: CY7C1910BV18, CY7C1310BV18. Please refer to the document for exact specifications by model.

Separate independent read and write data ports.
Supports concurrent transactions.
250 MHz clock for high bandwidth.
2-word burst on all accesses.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simp.

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Published: Nov 6, 2016 |