CY7C1303BV25 - 18-Mbit Burst of Two-Pipelined SRAM

Cypress Semiconductor

Datasheet Details

Part number	CY7C1303BV25
Manufacturer	Cypress Semiconductor
File Size	969.86 KB
Description	18-Mbit Burst of Two-Pipelined SRAM
Datasheet	CY7C1303BV25-CypressSemiconductor.pdf

Separate independent read and write data ports.
Supports concurrent transactions.
167 MHz clock for high bandwidth.
2.5 ns clock-to-valid access time.
Two word burst on all accesses.
Double data rate (DDR) interfaces on both read and write ports (data transferred at 333 MHz) at 167 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mism.

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Published: Nov 6, 2016 |