CY7C1304DV25 - 9-Mbit Burst of 4 Pipelined SRAM

Cypress Semiconductor

Datasheet Details

Part number	CY7C1304DV25
Manufacturer	Cypress Semiconductor
File Size	222.49 KB
Description	9-Mbit Burst of 4 Pipelined SRAM
Datasheet	CY7C1304DV25-CypressSemiconductor.pdf

Separate independent Read and Write data ports.
Supports concurrent transactions.
167-MHz Clock for high bandwidth.
2.5 ns Clock-to-Valid access time.
4-Word Burst for reducing the address bus frequency.
Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two output clocks (C and C) ac.

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Published: Nov 6, 2016 |