CDCVF310 buffer equivalent, 2.5-v to 3.3-v high-performance clock buffer.
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* High-Performance 1:10 Clock Driver
* Pin-to-Pin Skew < 100 ps at VDD 3.3 V
* VDD Range = 2.3 V to 3.6 V
* Input Clock Up To 200 MHz (See Figure 7)
* General-Purpose Applications
GND VDD 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VDD
1G 2Y4
PW PACKAGE (TOP VIEW)
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The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins..
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