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CDCVF2505 - 3.3-V Clock Phase-Lock Loop Clock Driver

General Description

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase.

Key Features

  • 1 Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCVF2505 SCAS640G – JULY 2000 – REVISED AUGUST 2016 CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver 1 Features •1 Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications • Spread Spectrum Clock Compatible • Operating Frequency: 24 MHz to 200 MHz • Low Jitter (Cycle-to-Cycle): < |150 ps| (Over 66 MHz to 200 MHz Range) • Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Used to Tune the Input-Output Delay) • Three-States Outputs When There Is No Input Clock • Operates From Single 3.