CDCVF2505 Overview
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
CDCVF2505 Key Features
- 1 Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose