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CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDCVF2509 Description

NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 www.ti.com SCAS737D * APRIL 2004 * REVISED FEBRUARY 2010.
The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

CDCVF2509 Features

* 1
* Use CDCVF2509A (SCAS765) as a Replacement for This Device
* Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
* Spread Spectrum Clock Compatible
* Operating Frequency 50 MHz to 175 MHz
* Static Phase Error Distribution at 66 MH

CDCVF2509 Applications

* Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
* Separate Output Enable for Each Output Bank
* External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
* 25-Ω On-Chip Series Damping Resistors
* No

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Texas Instruments CDCVF2509-like datasheet