CDCVF2509
Description
The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.
Key Features
- Use CDCVF2509A (SCAS765) as a Replacement for This Device
- Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
- Operating Frequency 50 MHz to 175 MHz
- Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps
- Jitter (cyc - cyc) at 66 MHz to 166 MHz Is Typ = 70 ps
- Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
- Available in Plastic 24-Pin TSSOP
- Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
- Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
- Separate Output Enable for Each Output Bank
