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CDCVF2509 - 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Datasheet Summary

Description

The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Features

  • 1.
  • Use CDCVF2509A (SCAS765) as a Replacement for This Device.
  • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1.
  • Spread Spectrum Clock Compatible.
  • Operating Frequency 50 MHz to 175 MHz.
  • Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps.
  • Jitter (cyc - cyc) at 66 MHz to 166 MHz Is Typ = 70 ps.
  • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Gener.

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Datasheet preview – CDCVF2509

Datasheet Details

Part number CDCVF2509
Manufacturer Texas Instruments
File Size 400.27 KB
Description 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Datasheet download datasheet CDCVF2509 Datasheet
Additional preview pages of the CDCVF2509 datasheet.

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Other Datasheets by Texas Instruments
  • CDCVF2509A - 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
  • CDCVF2505 - 3.3-V Clock Phase-Lock Loop Clock Driver
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Full PDF Text Transcription

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NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 www.ti.com SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 3.3-V PHASE-LOCK LOOP CLOCK DRIVER Check for Samples: CDCVF2509 FEATURES 1 • Use CDCVF2509A (SCAS765) as a Replacement for This Device • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.
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