CDCVF25081 driver equivalent, 3.3-v phased-lock loop clock driver.
* Phase-locked loop based, zero-delay buffer
– 1 clock input to 2 banks of 4 outputs
– No external RC network required
* Supply vo.
* Defense radio
* Production switchers and mixers
* Radar
* In-vitro diagnostics
* CT & PET scanner
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The CDCVF25081 is a high performance, low skew, low jitter, phased-locked loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The outputs are divided into 2 banks for a total.
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