CDCVF25081 Description
The CDCVF25081 is a high performance, low skew, low jitter, phased-locked loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The outputs are divided into 2 banks for a total of 8 buffered CLKIN outputs.
CDCVF25081 Key Features
- Phase-locked loop based, zero-delay buffer
- 1 clock input to 2 banks of 4 outputs
- No external RC network required
- Supply voltage: 3 V to 3.6 V
- Operating frequency: 8 MHz to 200 MHz
- Power-down mode available
- 25-Ω on-chip series damping resistors
- Industrial temperature range: -40°C to 85°C
- Spread Spectrum Clock patible (SSC)
- 9.9-mm × 3.91-mm, 16-pin SOIC (D)