CDCVF2510A driver equivalent, 3.3-v phase-lock loop clock driver.
1
* Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
* Spread Spectrum Clock Compatible
* Operating Frequency 20 MHz to 175 MHz .
* DRAM Applications
* PLL Based Clock Distributors
* Non-PLL Clock Buffer
PW PACKAGE (TOP VIEW)
AGND 1 VCC .
The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. .
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 425.08KB)