CDCVF2510 driver equivalent, 3.3-v phase-lock loop clock driver.
* Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
* Spread Spectrum Clock Compatible
* Operating Frequency 50 MHz to 175 MHz
* Distributes One Clock Input to One Bank of 10 Outputs
* External Feedback (FBIN) Terminal Is Used to Synchroni.
The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifi.
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