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Cypress Semiconductor Electronic Components Datasheet

CY7C1352F Datasheet

4-Mbit (256K x 18) Pipelined SRAM

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CY7C1352F
4-Mbit (256Kx18) Pipelined SRAM
with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• 2.5V / 3.3V I/O Operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep Mode Option and Stop Clock option
Logic Block Diagram
Functional Description[1]
The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352F is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.8 ns (200-MHz device)
Write operations are controlled by the two Byte Write Select
(BW[A:B]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
CLK
CEN
A0, A1, A
MODE
C
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPA
DQPB
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05211 Rev. *C
Revised April 16, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1352F Datasheet

4-Mbit (256K x 18) Pipelined SRAM

No Preview Available !

CY7C1352F
Selection Guide
250 MHz 225 MHz 200 MHz 166 MHz 133 MHz
Maximum Access Time
2.6 2.6 2.8 3.5 4.0
Maximum Operating Current
325 290 265 240 225
Maximum CMOS Standby Current
40
40
40
40
40
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of these parts.
100 MHz
4.5
205
40
Unit
ns
mA
mA
Pin Configuration
100-Pin TQFP
BYTE B
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1352F
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPA
73 DQA
72 DQA
71 VSS
70 VDDQ
69 DQA
68 DQA
67
VSS
BYTE A
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document #: 38-05211 Rev. *C
Page 2 of 13


Part Number CY7C1352F
Description 4-Mbit (256K x 18) Pipelined SRAM
Maker Cypress Semiconductor
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CY7C1352F Datasheet PDF






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