CY7C1351G
Overview
- Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock
- Pin compatible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow-through operation
- Byte write capability
- 128 K × 36 common I/O architecture
- 2.5 V/3.3 V I/O power supply (VDDQ)
- Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device)
- Clock enable (CEN) pin to suspend operation
- Synchronous self-timed writes
