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Cypress Semiconductor Electronic Components Datasheet

CY7C1353 Datasheet

256Kx18 Flow-Through SRAM

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CY7C1353
256Kx18 Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
Pin compatible and functionally equivalent to ZBT
devices MCM63Z819 and MT55L256L18F
• Supports 66-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 11.0 ns (for 66-MHz device)
— 12.0 ns (for 50-MHz device)
— 14.0 ns (for 40-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power
The CY7C1353 is a 3.3V 256K by 18 Synchronous-
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353 is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutive Read/Write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems
that require frequent Write-Read transitions.The CY7C1353 is
pin/functionally compatible to ZBTSRAMs MCM63Z819 and
MT55L256L18F.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 9.0 ns (66-MHz de-
vice).
Write operations are controlled by the four Byte Write Select
(BWS[1:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
ADV/LD
A[17:0]
CEN
CE1
CE 2
CE 3
WE
BWS [1:0]
Mode
18
CONTROL
and WRITE
LOGIC
CE
DaDta-In
Q
REG.
18
18
256KX18
18
MEMORY
18 ARRAY
DQ[15:0]
DP[1:0]
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Maximum CMOS Standby Current (mA)
Commercial
NoBL is a trademark of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
7C1353-66
11
250 mA
5 mA
7C1353-50
12.0
200 mA
5 mA
7C1353-40
14.0
175 mA
5 mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 3, 1999


Cypress Semiconductor Electronic Components Datasheet

CY7C1353 Datasheet

256Kx18 Flow-Through SRAM

No Preview Available !

Pin Configuration
NC
NC
NC
VDDQ
VSS
NC
NC
DQ8
DQ9
VSS
VDDQ
DQ10
DQ11
VSS
VDD
VDD
VSS
DQ12
DQ13
VDDQ
VSS
DQ14
DQ15
DP1
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-Pin TQFP
CY7C1353
CY7C1353
80 A17
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DP0
73 DQ7
72 DQ6
71 VSS
70 VDDQ
69 DQ5
68 DQ4
67 VSS
66 VSS
65 VDD
64 VSS
63 DQ3
62 DQ2
61 VDDQ
60 VSS
59 DQ1
58 DQ0
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
2


Part Number CY7C1353
Description 256Kx18 Flow-Through SRAM
Maker Cypress Semiconductor
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CY7C1353 Datasheet PDF






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