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Cypress Semiconductor Electronic Components Datasheet

CY7C1352 Datasheet

256K x18 Pipelined SRAM

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CY7C1352
256K x18 Pipelined SRAM with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT™
devices MCM63Z818 and MT55L256L18P
• Supports 143-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write Capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 4.0 ns (for 143-MHz device)
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
— 7.0 ns (for 80-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description
The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352 is equipped with the advanced No
Bus Latency™ (NoBL™) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of the SRAM, especially in systems that require frequent
Read/Write transitions.The CY7C1352 is pin/functionally com-
patible to ZBT™ SRAMs MCM63Z819 and MT55L256L18P.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
4.0 ns (143-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS[1:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
ADV/LD
A[17:0]
CEN
CE1
CE2
CE3
WE
BWS [1:0]
Mode
18
CONTROL
and WRITE
LOGIC
CE
DaDta-In
Q
REG.
18
18
256Kx18
18
MEMORY
18 ARRAY
18
DQ[15:0]
DP[1:0]
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
.
Commercial
Commercial
7C1352-143
4.0
450
5
7C1352-133
4.2
400
5
7C1352-100
5.0
350
5
7C1352-80
7.0
300
5
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 9, 1999


Cypress Semiconductor Electronic Components Datasheet

CY7C1352 Datasheet

256K x18 Pipelined SRAM

No Preview Available !

Pin Configuration
100-Pin TQFP
CY7C1352
NC
NC
NC
VDDQ
VSS
NC
NC
DQ8
DQ9
VSS
VDDQ
DQ10
DQ11
VDDQ
VDD
VDD
VSS
DQ12
DQ13
VDDQ
VSS
DQ14
DQ15
DP1
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1352
80 A17
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DP0
73 DQ7
72 DQ6
71 VSS
70 VDDQ
69 DQ5
68 DQ4
67 VSS
66 VDD
65 VDD
64 VSS
63 DQ3
62 DQ2
61 VDDQ
60 VSS
59 DQ1
58 DQ0
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
2


Part Number CY7C1352
Description 256K x18 Pipelined SRAM
Maker Cypress Semiconductor
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CY7C1352 Datasheet PDF






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