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Cypress Semiconductor Electronic Components Datasheet

CY7C1352G Datasheet

4-Mbit (256K x 18) Pipelined SRAM

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CY7C1352G
4-Mbit (256K × 18) Pipelined SRAM
with NoBL™ Architecture
4-Mbit (256K × 18) Pipelined SRAM with NoBL™ Architecture
Features
Pin compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need
to use OE
Byte write capability
256K × 18 common I/O architecture
3.3 V core power supply (VDD)
2.5 V/3.3 V I/O power supply (VDDQ)
Fast clock-to-output times
4.0 ns (for 133-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable (OE)
Available in Pb-free 100-pin TQFP package
Burst capability – linear or interleaved burst order
ZZ sleep mode option and stop clock option
Functional Description
The CY7C1352G is a 3.3 V, 256K × 18 synchronous-pipelined
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1352G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of the
SRAM, especially in systems that require frequent write/read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which, when
deasserted, suspends operation and extends the previous clock
cycle. Maximum access delay from the clock rise is 4.0 ns
(133-MHz device).
Write operations are controlled by the two byte write select
(BW[A:B]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz
4.0
225
40
Unit
ns
mA
mA
Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05514 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 3, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1352G Datasheet

4-Mbit (256K x 18) Pipelined SRAM

No Preview Available !

CY7C1352G
Logic Block Diagram – CY7C1352G
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1 Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
DQs
DQPA
DQPB
INPUT
REGISTER 1 E
INPUT
REGISTER0 E
OE
CE1 READ LOGIC
CE2
CE3
ZZ
Sleep
Control
Document Number: 38-05514 Rev. *O
Page 2 of 22


Part Number CY7C1352G
Description 4-Mbit (256K x 18) Pipelined SRAM
Maker Cypress Semiconductor
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CY7C1352G Datasheet PDF






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