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Cypress Semiconductor Electronic Components Datasheet

CY7C1351F Datasheet

4-Mb (128K x 36) Flow-through SRAM

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CY7C1351F
4-Mb (128K x 36) Flow-through SRAM with
NoBL™ Architecture
Features
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 128K x 36 common I/O architecture
• 2.5V / 3.3V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
— 8.0 ns (for 100-MHz device)
— 11.0 ns (for 66-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP and 119 BGA packages
Logic Block Diagram
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description[1]
The CY7C1351F is a 3.3V, 128K x 36 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1351F is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the four Byte Write Select
(BW[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
CLK
CEN
A0, A1, A
MODE
C
CE
ADV/LD
BWA
BWB
BWC
BWD
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
READ LOGIC
SLEEP
Control
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQPA
DQPB
DQPC
DQPD
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05210 Rev. *B
Revised January 12, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1351F Datasheet

4-Mb (128K x 36) Flow-through SRAM

No Preview Available !

Selection Guide
133 MHz
117 MHz
100 MHz
Maximum Access Time
6.5 7.5 8.0
Maximum Operating Current
225 220 205
Maximum CMOS Standby Current
40 40 40
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
100-lead TQFP
CY7C1351F
66 MHz
11.0
195
40
Unit
ns
mA
mA
BYTE C
BYTE D
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1351F
80 DQPB
79 DQB
78 DQB
77 VDDQ
76 VSS
75 DQB
74 DQB BYTE B
73 DQB
72 DQB
71 VSS
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57 DQA BYTE A
56 DQA
55 VSS
54 VDDQ
53 DQA
52 DQA
51 DQPA
Document #: 38-05210 Rev. *B
Page 2 of 15


Part Number CY7C1351F
Description 4-Mb (128K x 36) Flow-through SRAM
Maker Cypress Semiconductor
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CY7C1351F Datasheet PDF






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