CY7C1311BV18 Overview
QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to pletely eliminate the need to “turn-around” the data bus required with mon I/O devices.
CY7C1311BV18 Key Features
- Separate Independent Read and Write data ports
- Supports concurrent transactions
- 300-MHz clock for high bandwidth
- 4-Word Burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Single multiplexed address input bus latches address inputs for both Read and Write ports