CY7C1311AV18 architecture equivalent, (cy7c131xav18) 18-mb qdrtm-ii sram 4-word burst architecture.
* Separate Independent Read and Write Data Ports — Supports concurrent transactions
* 250-MHz Clock for High Bandwidth
* 4-Word Burst for reducing address bus.
The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Rea.
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