Datasheet4U Logo Datasheet4U.com

CY7C1320AV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Download the CY7C1320AV18 datasheet PDF. This datasheet also covers the CY7C1316AV18 variant, as both devices belong to the same 18-mbit ddr-ii sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture.

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Features

  • 18-Mb density (2M x 8, 1M x 18, 512K x 36).
  • 250-MHz clock for high bandwidth.
  • 2-Word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two output clocks (C and C) account for clock skew and flight time mismatching.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed syste.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1316AV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C131AE 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C131E 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C136AE 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C136E 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320CV18 (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C132 2K x 8 Dual-Port Static RAM

Full PDF Text Transcription

Click to expand full text
CY7C1316AV18 CY7C1318AV18 CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features • 18-Mb density (2M x 8, 1M x 18, 512K x 36) • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) account for clock skew and flight time mismatching • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix) • JTAG 1149.
Published: |