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CY7C1320BV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Download the CY7C1320BV18 datasheet PDF. This datasheet also covers the CY7C1316BV18 variant, as both devices belong to the same 18-mbit ddr-ii sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture.

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Features

  • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36).
  • 300-MHz clock for high bandwidth.
  • 2-Word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
  • Echo clocks (CQ and CQ) simplify data cap.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1316BV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320CV18 (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture
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Full PDF Text Transcription

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CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • Available in 165-ball FBGA package (13 x 15 x 1.
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