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CY7C1320KV18 - 18-Mbit DDR II SRAM Two-Word Burst Architecture

Download the CY7C1320KV18 datasheet PDF. This datasheet also covers the CY7C1316KV18 variant, as both devices belong to the same 18-mbit ddr ii sram two-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and CY7C1320KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture.

The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Features

  • Configurations CY7C1316KV18.
  • 2 M × 8 CY7C1916KV18.
  • 2 M × 9 CY7C1318KV18.
  • 1 M × 18 CY7C1320KV18.
  • 512 K × 36 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36) 333-MHz clock for high bandwidth Two-word burst for reducing address bus frequency Double data rate (DDR) interfaces  (data transferred at 666 MHz) at 333 MHz Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only Two input clocks for out.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1316KV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
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Full PDF Text Transcription

Click to expand full text
 CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features ■ ■ ■ ■ ■ Configurations CY7C1316KV18 – 2 M × 8 CY7C1916KV18 – 2 M × 9 CY7C1318KV18 – 1 M × 18 CY7C1320KV18 – 512 K × 36 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36) 333-MHz clock for high bandwidth Two-word burst for reducing address bus frequency Double data rate (DDR) interfaces  (data transferred at 666 MHz) at 333 MHz Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Synchronous internally self-timed writes DDR II operate
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