Datasheet4U Logo Datasheet4U.com

CY7C1320CV18 - (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Download the CY7C1320CV18 datasheet PDF. This datasheet also covers the CY7C1316CV18 variant, as both devices belong to the same (cy7c1xxxcv18) 18-mbit ddr-ii sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture.

The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1316CV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C131AE 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C131E 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C136AE 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C136E 1K/2K x 8 Dual-Port Static RAM Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C132 2K x 8 Dual-Port Static RAM

Full PDF Text Transcription

Click to expand full text
CY7C1316CV18, CY7C1916CV18 CY7C1318CV18, CY7C1320CV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided.
Published: |