CY7C1311KV18 - 18-Mbit QDR II SRAM Four-Word Burst Architecture

Name: CY7C1311KV18
SKU: CY7C1311KV18-1101445

Cypress Semiconductor

The CY7C1311KV18 by Cypress Semiconductor is a 18-Mbit QDR II SRAM Four-Word Burst Architecture. Below is the official datasheet preview.

Datasheet Details

Part number	CY7C1311KV18
Manufacturer	Cypress Semiconductor
File Size	657.31 KB
Description	18-Mbit QDR II SRAM Four-Word Burst Architecture
Datasheet	CY7C1311KV18-CypressSemiconductor.pdf
Additional preview pages of the CY7C1311KV18 datasheet.

Separate independent read and write data ports.
Supports concurrent transactions.
333-MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches.
Echo cl.

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Published: Mar 14, 2017 |