CY7C1312BV18 Datasheet

Manufacturer: Cypress (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C1312BV18
Datasheet	CY7C1312BV18 CY7C1310BV18 Datasheet (PDF)
File Size	390.16 KB
Manufacturer	Cypress (now Infineon)
Description	1.8V Synchronous Pipelined SRAM

CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit QDR™-II SRAM 2-Word Burst Architecture.

Separate independent read and write data ports
Supports concurrent transactions
250 MHz clock for high bandwidth
2-word burst on all accesses
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed systems
Single multiplexed address input bus latches address inputs for both read and write ports

Part Number	Description
CY7C1312KV18	18-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C131	1K x 8 Dual-Port Static RAM
CY7C1310BV18	1.8V Synchronous Pipelined SRAM
CY7C1311AV18	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311BV18	(CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311CV18	(CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311JV18	(CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1311KV18	18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1313AV18	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1313BV18	(CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture