Datasheet4U Logo Datasheet4U.com

CY7C1312KV18 - 18-Mbit QDR II SRAM Two-Word Burst Architecture

Datasheet Summary

Description

The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture.

QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 333 MHz clock for high bandwidth.
  • Two-word burst on all accesses.
  • Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) sim.

📥 Download Datasheet

Datasheet preview – CY7C1312KV18

Datasheet Details

Part number CY7C1312KV18
Manufacturer Cypress Semiconductor
File Size 790.78 KB
Description 18-Mbit QDR II SRAM Two-Word Burst Architecture
Datasheet download datasheet CY7C1312KV18 Datasheet
Additional preview pages of the CY7C1312KV18 datasheet.

📁 Similar Datasheet

  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
  • CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
  • CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C1312BV18 - 1.8V Synchronous Pipelined SRAM
  • CY7C131 - 1K x 8 Dual-Port Static RAM
  • CY7C1310BV18 - 1.8V Synchronous Pipelined SRAM
  • CY7C1311AV18 - (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
  • CY7C1311BV18 - (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
  • CY7C1311CV18 - (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
  • CY7C1311JV18 - (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
  • CY7C1311KV18 - 18-Mbit QDR II SRAM Four-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally
Published: |