| Part number | CY7C1311JV18 |
|---|---|
| Datasheet | CY7C1311JV18_CypressSemiconductor.pdf |
| File Size | 705.07 KB |
| Manufacturer | Cypress (now Infineon) |
| Description | (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture |
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QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
See all Cypress (now Infineon) datasheets
| Part Number | Description |
|---|---|
| CY7C1311AV18 | (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture |
| CY7C1311BV18 | (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture |
| CY7C1311CV18 | (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture |
| CY7C1311KV18 | 18-Mbit QDR II SRAM Four-Word Burst Architecture |
| CY7C131 | 1K x 8 Dual-Port Static RAM |
| CY7C1310BV18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1312BV18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1312KV18 | 18-Mbit QDR II SRAM Two-Word Burst Architecture |
| CY7C1313AV18 | (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture |
| CY7C1313BV18 | (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture |
