CY7C1312KV18
Description
× 18 × 36 333 MHz 333 690 840 300 MHz 300 640 780 250 MHz 250 560 670 Unit MHz mA Cypress Semiconductor Corporation - 198 Champion Court Document Number: 001-58903 Rev.
Key Features
- Separate independent read and write data ports ❐ Supports concurrent transactions
- 333 MHz clock for high bandwidth
- Two-word burst on all accesses
- Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
- Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Single multiplexed address input bus latches address inputs for both read and write ports
- Separate port selects for depth expansion
- Synchronous internally self-timed writes
