CY7C1312KV18 Datasheet 18-mbit Qdr Ii Sram Two-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst.

Datasheet Details

Part number	CY7C1312KV18
Manufacturer	Cypress (now Infineon)
File Size	790.78 KB
Description	18-Mbit QDR II SRAM Two-Word Burst Architecture
Datasheet	CY7C1312KV18-CypressSemiconductor.pdf

The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture.

QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.

The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

Separate independent read and write data ports.
Supports concurrent transactions.
333 MHz clock for high bandwidth.
Two-word burst on all accesses.
Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) sim.

Part Number	Description
CY7C1312BV18	1.8V Synchronous Pipelined SRAM
CY7C131	1K x 8 Dual-Port Static RAM
CY7C1310BV18	1.8V Synchronous Pipelined SRAM
CY7C1311AV18	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311BV18	(CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311CV18	(CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311JV18	(CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1311KV18	18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1313AV18	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1313BV18	(CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture