CY7C1312KV18 architecture equivalent, 18-mbit qdr ii sram two-word burst architecture.
* Separate independent read and write data ports
* Supports concurrent transactions
* 333 MHz clock for high bandwidth
* Two-word burst on all accesses
The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated .
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