CY7C1312KV18 Description
The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.
CY7C1312KV18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 333 MHz clock for high bandwidth
- Two-word burst on all accesses
- Double-data rate (DDR) interfaces on both read and write ports
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock
- Echo clocks (CQ and CQ) simplify data capture in high-speed
- Single multiplexed address input bus latches address inputs