Cypress CY7 Datasheet | Specifications & PDF Download

CY7C1370KV25 CY7C1372KV25 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Ar

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CY7C1041G CY7C1041GE 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words × 16 bit) Static RAM with Error-Corr

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CY7C4255V CY7C4275V CY7C4285V 8K/32K/64K × 18 Low Voltage Deep Sync FIFOs 8K/32K/64K × 18 Low Voltage Deep Sync FIFOs Features ■ 3.3 V operation for

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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Features • High-speed, low-power, first-in

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512 K × 8 Static RAM Features ■ High speed ❐ tAA = 17 ns ■ Low active power ❐ 1073 mW (max.) ■ Low CMOS standby power ❐ 2.75 mW (max.) ■ 2.0 V data re

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CY7C1378C 9-Mbit (256K x 32) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT® devices • Internall

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CY7C4425/4205/4215 CY7C4225/4235/4245 64/256/512/1K/2K/4K x 18 Synchronous FIFOs Features ■ High speed, low power, first-in first-out (FIFO) memories

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CY7C1380S CY7C1382S 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features ■ Supports bus operation up to

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CY7C1041BN 256K × 16 Static RAM 256K × 16 Static RAM Features ■ Temperature range: ❐ Commercial: 0 °C to 70 °C ❐ Automotive-A: –40 °C to 85 °C ■ High

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CY7C1386KV33 CY7C1387KV33 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM Features ■ Supports

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CY7C13451G 4-Mbit (128K × 36) Flow-Through Sync SRAM 4-Mbit (128K × 36) Flow-Through Sync SRAM Features ■ 128K × 36 common I/O ■ 3.3 V core Power Sup

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CY7C1380DV33 CY7C1382DV33 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features ■ Supports bus operation

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Not Recommended for New Designs. CY7C1380D CY7C1380F CY7C1382D 18-Mbit (512K × 36/1M × 18) Pipelined SRAM 18-Mbit (512K × 36/1M × 18) Pipelined SRAM

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CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features ■ 36-Mbit

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CY7C107D CY7C1007D 1-Mbit (1 M × 1) Static RAM 1-Mbit (1 M × 1) Static RAM Features ■ Pin- and function-compatible with CY7C107B/CY7C1007B ■ High spe

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CY7C1049G CY7C1049GE 4-Mbit (512K words × 8 bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (512K words × 8 bit) Static RAM with Error-Correc

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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Features • High-speed, low-power, first-in

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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Features • High-speed, low-power, first-in

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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Features • High-speed, low-power, first-in

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