CY7C1372B Datasheet PDF - Cypress Semiconductor (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM Specs

CY7C1372B - (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

This page provides the datasheet information for the CY7C1372B, a member of the CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM family.

Datasheet Summary

Description

The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa.

These SRAMs are optimized for 100 percent bus utilization and achieve Zero Bus Latency.

Features

Zero Bus Latency, no dead cycles between Write and Read cycles.
Fast clock speed: 200, 167, 150, and 133 MHz.
Fast access time: 3.0, 3.4, 3.8, and 4.2 ns.
Internally synchronized registered outputs eliminate the need to control OE.
Single 3.3V.
5% and +10% power supply VDD.
Separate VDDQ for 3.3V or 2.5V I/O.
Single WE (Read/Write) control pin.
Positive clock-edge triggered address, data, and control signal register.

Datasheet Details

Part number	CY7C1372B
Manufacturer	Cypress Semiconductor
File Size	811.36 KB
Description	(CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
Datasheet	CY7C1372B Datasheet
Additional preview pages of the CY7C1372B datasheet.

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Full PDF Text Transcription

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CY7C1370B CY7C1372B 512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +10% power supply VDD • Separate VDDQ for 3.3V or 2.

Published: Jan 25, 2010 |