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CY7C1265V18 - 1.8V Synchronous Pipelined SRAM

Download the CY7C1265V18 datasheet PDF. This datasheet also covers the CY7C1261V18 variant, as both devices belong to the same 1.8v synchronous pipelined sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 300 MHz to 400 MHz clock for high bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz.
  • Read latency of 2.5 clock cycles.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1261V18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C1261V18 1.8V Synchronous Pipelined SRAM
CY7C1262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C1263KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth ■ 4-Word Burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz ■ Read latency of 2.
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