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CY7C1380BV25 - 512K x 36 / 1 Mb x 18 Pipelined SRAM

Download the CY7C1380BV25 datasheet PDF. This datasheet also covers the CY7 variant, as both devices belong to the same 512k x 36 / 1 mb x 18 pipelined sram family and are provided as variant models within a single manufacturer datasheet.

Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology.

Each memory cell consists of six transistors.

Features

  • Fast clock speed: 200,166, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns Optimal for depth expansion 2.5V (±5%) Operation Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed WRITE CYCLE Burst control pins (inter.

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Note: The manufacturer provides a single datasheet file (CY7-C1380.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1380S 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM Cypress
CY7C1381D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM Cypress
CY7C1382S 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM Cypress
CY7C1383D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM Cypress
CY7C1383F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1380C 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380CV25 (CY7C1380CV25 / CY7C1382CV25) 512K x 36/1M x 18 Pipelined SRAM
CY7C1380D 18-Mbit Pipelined SRAM
CY7C1380DV33 18-Mbit Pipelined SRAM
CY7C1380F 18-Mbit Pipelined SRAM

Full PDF Text Transcription

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1CY7C1380BV25 PRELIMINARY CY7C1380BV25 CY7C1382BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200,166, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns Optimal for depth expansion 2.5V (±5%) Operation Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed WRITE CYCLE Burst control pins (interleaved or linear burst sequence) • Automatic power-down for portable applications • High-density, high-speed packages • JTAG boundary scan for BGA packaging version (CLK).
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