CDCLVP111 Datasheet PDF - Texas Instruments Low-Voltage 1:10 LVPECL Specs

CDCLVP111 - Low-Voltage 1:10 LVPECL

Datasheet Summary

Description

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution.

The CDCLVP111 can accept two clock sources into an input multiplexer.

Features

1 Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL.
Fully Compatible With LVECL and LVPECL.
Supports a Wide Supply Voltage Range from 2.375 V to 3.8 V.
Selectable Clock Input Through CLK_SEL.
Low-Output Skew (Typical 15 ps) for Clock- Distribution.

Datasheet Details

Part number	CDCLVP111
Manufacturer	Texas Instruments
File Size	2.39 MB
Description	Low-Voltage 1:10 LVPECL
Datasheet	CDCLVP111 Datasheet
Additional preview pages of the CDCLVP111 datasheet.

📁 Similar Datasheet

CDCLD080 - SURFACE MOUNT SILICON CURRENT LIMITING DIODES (Central Semiconductor)

CDCLD100 - SURFACE MOUNT SILICON CURRENT LIMITING DIODES (Central Semiconductor)

CDCLD120 - SURFACE MOUNT SILICON CURRENT LIMITING DIODES (Central Semiconductor)

CDCLD200 - SURFACE MOUNT SILICON CURRENT LIMITING DIODES (Central Semiconductor)

CDCLD400 - SURFACE MOUNT SILICON CURRENT LIMITING DIODES (Central Semiconductor)

CDCLD500 - SURFACE MOUNT SILICON CURRENT LIMITING DIODES (Central Semiconductor)

CDC-Z137 - FM / AM CD Player (Aiwa)

CDC1607F-E - Automotive Controller Specification (Micronas)

CDC1631F-E - Automotive Controller (Micronas)

CDC3207G-C - Automotive Controller (Micronas)

Full PDF Text Transcription

Click to expand full text

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVP111 SCAS859F – JANUARY 2009 – REVISED JUNE 2015 CDCLVP111 Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver 1 Features •1 Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL • Fully Compatible With LVECL and LVPECL • Supports a Wide Supply Voltage Range from 2.375 V to 3.8 V • Selectable Clock Input Through CLK_SEL • Low-Output Skew (Typical 15 ps) for Clock- Distribution Applications – Additive Jitter Less Than 1 ps – Propagation Delay Less Than 350 ps – Open Input Default State – LVDS, CML, SSTL Input Compatible • VBB Reference Voltage Output for Single-Ended Clocking • Available in a 32-Pin LQFP and QFN Package • Frequency Range From DC to 3.

Published: Jul 6, 2023 |