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74AC11378 - HEX D-TYPE FLIP-FLOP

Description

These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the clock-enable input (CLKEN) is low.

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Full PDF Text Transcription

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• Contains Six D-Type Flip-Flops • Clock Enable Latched to Avoid False Clocking • Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise • EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process • 500-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic Small-Outline Packages, and Standard Plastic 300-mil DIPs 74AC11378 HEX D–TYPE FLIP–FLOP WITH CLOCK ENABLE SCAS150 – APRIL 1991 – REVISED APRIL 1993 DW OR N PACKAGE (TOP VIEW) 1Q 2Q 3Q GND GND GND GND 4Q 5Q 6Q 1 2 3 4 5 6 7 8 9 10 20 CLKEN 19 1D 18 2D 17 3D 16 VCC 15 VCC 14 4D 13 5D 12 6D 11 CLK description These circuits are positive-edge-triggered D-type fli
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