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74AC11352 - Dual 4-Line to 1-Line Data Selector/Multiplexer

Description

Each of these data selectors/multiplexers contains inverters and drivers to supply full binary-decoding data selection to the AND-OR gates.

Separate strobe output-enable (OE) inputs are provided for each of the two four-line sections.

40°C

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Full PDF Text Transcription

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74AC11352 DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER • Permit Multiplexing from N Lines to 1 Line • Perform Parallel-to-Serial Conversion • Strobe Line Provided for Cascading (N Lines to N Lines) • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise • EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process • 500-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic Small-Outline Packages, and Standard Plastic 300-mil DIPs SCAS167 − DECEMBER 1991 − REVISED APRIL 1993 D OR N PACKAGE (TOP VIEW) A B 1Y GND 2Y 1OE 2OE 2C3 1 2 3 4 5 6 7 8 16 1C0 15 1C1 14 1C2 13 1C3 12 VCC 11 2C0 10 2C1 9 2C2 description Each of these data selectors/multiplexers contains inverters and drivers to supply full
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