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74AC11353 - DUAL 1-OR-4 DATA SELECTOR/MULTIPLEXER

Description

Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates.

Separate strobe output-enable (1OE or 2OE) inputs are provided for each of the two four-line sections.

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Full PDF Text Transcription

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74AC11353 DUAL 1–OR–4 DATA SELECTOR/MULTIPLEXER • Inverting Version of 74AC11253 • Permits Multiplexing from N Lines to 1 Line • Performs Parallel-to-Serial Conversion • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process • Package Options Include Plastic Small-Outline Packages, and Standard Plastic 300-mil DIPs SCAS044A – JUNE 1988 – REVISED APRIL 1993 D OR N PACKAGE (TOP VIEW) A B 1Y GND 2Y 1OE 2OE 2C3 1 2 3 4 5 6 7 8 16 1C0 15 1C1 14 1C2 13 1C3 12 VCC 11 2C0 10 2C1 9 2C2 description Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates.
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