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H5DU6462CTR - 64Mb DDR SDRAM

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333 and 400) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL.

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www.DataSheet4U.com 64Mb DDR SDRAM H5DU6462CTR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 /July. 2008 1 Release H5DU6462CTR Series Revision History Revision No. 0.1 First version 1. Correct 1-1. tCK (max @E3, K2, K3) : 12ns -> 10ns 0.2 2. Delete 2-1. Ordering information K3@CL2 (100Mhz) 3. ADd 3-1. Ordering information : -FA (DDR500 4-4-4) 3-2. AC/DC Characteristic : -FA (DDR500 4-4-4) 1.0 1. Release July. 2008 Apr. 2008 Preliminary History Draft Date Apr. 2008 Remark Preliminary www.DataSheet4U.com Rev. 1.0 /July. 2008 2 Release H5DU6462CTR Series www.DataSheet4U.
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