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H5DU2562GFR - 256Mb DDR SDRAM

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL ali.

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Full PDF Text Transcription

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www.DataSheet4U.com 256Mb DDR SDRAM H5DU2562GFR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 /Sep. 2009 1 www.DataSheet4U.com H5DU2562GFR Revision History Revision No. 0.1 0.2 1.0 1.1 History Preliminary Revised tRC, tWR spec @ DDR500 Release Revised Operating Frequency Draft Date Jun. 2009 Jun. 2009 Jul. 2009 Sep. 2009 Remark Rev. 1.1 /Sep. 2007 2 www.DataSheet4U.com H5DU2562GFR DESCRIPTION The H5DU2562GFR is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
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