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H5DU2582GTR - (H5DU2562GTR / H5DU2582GTR) 256Mb DDR SDRAM

Download the H5DU2582GTR datasheet PDF. This datasheet also covers the H5DU2562GTR variant, as both devices belong to the same (h5du2562gtr / h5du2582gtr) 256mb ddr sdram family and are provided as variant models within a single manufacturer datasheet.

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL ali.

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Note: The manufacturer provides a single datasheet file (H5DU2562GTR_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number H5DU2582GTR
Manufacturer SK Hynix
File Size 425.37 KB
Description (H5DU2562GTR / H5DU2582GTR) 256Mb DDR SDRAM
Datasheet download datasheet H5DU2582GTR Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.com 256Mb DDR SDRAM H5DU2562GTR H5DU2582GTR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Sep. 2009 1 www.DataSheet4U.com H5DU2562GTR H5DU2582GTR Revision History Revision No. 0.1 0.2 1.0 1.1 Preliminary Revised tRC, tWR spec @ DDR500 Release Revised Operating Frequency History Draft Date Jun. 2009 Jun. 2009 Jul. 2009 Sep. 2009 Remark Rev. 1.1 / Sep. 2009 2 www.DataSheet4U.
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