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H5DU1262GTR - 128Mb DDR SDRAM

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333 ,400 and 500) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chi.

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www.DataSheet4U.com 128Mb DDR SDRAM H5DU1262GTR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / May 2009 1 www.DataSheet4U.com H5DU1262GTR Series Revision History Revision No. 0.1 1.0 First version Release History Draft Date Feb. 2009 May 2009 Remark PPre Rev. 1.0 / May 2009 2 www.DataSheet4U.com H5DU1262GTR Series PPre DESCRIPTION The H5DU1262GTR is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
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