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HD74HC76 - Dual J-K Flip-Flops (with Preset and Clear)

Description

Each flip-flop has independent J, K, preset, clear, and clock inputs and Q and Q outputs.

This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.

Features

  • High Speed Operation: tpd (Clock to Q) = 21 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Inputs Preset L H L H H H H H H H Note: Clear H L L H H H H H H H L H Clock X X X J X X X L L H H X X X K X X X L H L H X X X Outputs Q H L H.
  • 1 Q L H H.
  • 1 No change L H Toggle No ch.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC76 Dual J-K Flip-Flops Renesas
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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC73 Dual J-K Flip-Flops (with Clear)
HD74HC74 Dual D-type Flip-Flops (with Preset and Clear)
HD74HC75 Quad. Bistable Latches
HD74HC77 4-bit Bistable Latch
HD74HC78 Dual J-K Flip-Flops (with Preset/ Common Clear and Common Clock)

Full PDF Text Transcription

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HD74HC76 Dual J-K Flip-Flops (with Preset and Clear) Description Each flip-flop has independent J, K, preset, clear, and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input.
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