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HD74HC74 - Dual D-type Flip-Flops (with Preset and Clear)

Description

The flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.

Each flip-flop has independent, J, K, clock, and clear inputs and Q and Q outputs.

Clear is independent of the clock and accomplished by a low level on the input.

Features

  • High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Inputs Clear L H H H H H H H L H Clock X J X L L H H X X X K X L H L H X X X Outputs Q L No change L H Toggle No change No change No change H L Q H HD74HC73 Pin Arrangement 1CK 1 CLR 1CLR 2.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC74 Dual D-type Flip-Flops Renesas
HD74HC73 Dual J-K Flip-Flops Renesas
HD74HC75 Quad. Bistable Latches Renesas
HD74HC76 Dual J-K Flip-Flops Renesas
HD74HC77 4-bit Bistable Latch Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC73 Dual J-K Flip-Flops (with Clear)
HD74HC75 Quad. Bistable Latches
HD74HC76 Dual J-K Flip-Flops (with Preset and Clear)
HD74HC77 4-bit Bistable Latch
HD74HC78 Dual J-K Flip-Flops (with Preset/ Common Clear and Common Clock)

Full PDF Text Transcription

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HD74HC73 Dual J-K Flip-Flops (with Clear) Description The flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each flip-flop has independent, J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input.
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