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HD74HC73 - Dual J-K Flip-Flops (with Clear)

Description

The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs.

The logic level present at thte data input is transferred to the output during the positive going transition to the clock pulse.

Features

  • High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Inputs Preset L H L H H H H H Note: Clear H L L H H H H H L H Clock X X X Data X X X H L X X X Outputs Q H L H.
  • H L no change no change no change 1 Q L H H.
  • 1 L H no change no ch.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC73 Dual J-K Flip-Flops Renesas
HD74HC74 Dual D-type Flip-Flops Renesas
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HD74HC76 Dual J-K Flip-Flops Renesas
HD74HC77 4-bit Bistable Latch Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC74 Dual D-type Flip-Flops (with Preset and Clear)
HD74HC75 Quad. Bistable Latches
HD74HC76 Dual J-K Flip-Flops (with Preset and Clear)
HD74HC77 4-bit Bistable Latch
HD74HC78 Dual J-K Flip-Flops (with Preset/ Common Clear and Common Clock)

Full PDF Text Transcription

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HD74HC74 Dual D-type Flip-Flops (with Preset and Clear) Description The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at thte data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input.
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