Datasheet4U Logo Datasheet4U.com

HD74ALVCH16500 - 18-bit Universal Bus Transceivers with 3-state Outputs

Description

Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock ( CLKAB and CLKBA) inputs.

For A to B data flow, the device operates in the transparent mode when LEAB is high.

Features

  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • High output current ±24 mA (@V CC = 3.0 V).
  • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors HD74ALVCH16500 Function Table.
  • 3 Inputs OEAB L H H H H H H LEAB X H H L L L L CLKAB X X X ↓ ↓ H L A X L H L H X X Z L H L H B0 B0.
  • 1.
  • 2 Output B H : High level L : Low l.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74ALVCH16501 18-bit Universal Bus Transceivers Renesas
HD74ALVCH162244 16-bit Buffers / Drivers Renesas
HD74ALVCH162270 12-bit to 24-bit Registered Bus Exchanger Renesas
HD74ALVCH16244 16-bit Buffers / Drivers Renesas
HD74ALVCH16245 6-bit Bus Transceivers Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74ALVCH16501 18-bit Universal Bus Transceivers with 3-state Outputs
HD74ALVCH16543 16-bit Registered Transceivers with 3-state Outputs
HD74ALVCH162244 16-bit Buffers / Drivers with 3-state Outputs
HD74ALVCH162260 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
HD74ALVCH162270 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs

Full PDF Text Transcription

Click to expand full text
HD74ALVCH16500 18-bit Universal Bus Transceivers with 3-state Outputs ADE-205-167A (Z) 2nd. Edition December 1999 Description Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock ( CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the high to low transition of CLKAB. Output enable OEAB is active high. When OEAB is high, the B port outputs are active. When OEAB is low, the B port outputs are in the high impedance state. Data flow for B to A is similar to that of A to B but uses OEBA , LEBA, and CLKBA.
Published: |