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HD74ALVCH162260 - 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs

Description

The HD74ALVCH162260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path.

Features

  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • High output current ±12 mA (@V CC = 3.0 V).
  • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors.
  • B-port outputs have equivalent 26 Ω series resistors, so no external resistors are required. HD74ALVCH162260 Function Table Inputs 1B H L X X X X X 2B X X X H L X X SEL H H.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74ALVCH162244 16-bit Buffers / Drivers Renesas
HD74ALVCH162270 12-bit to 24-bit Registered Bus Exchanger Renesas
HD74ALVCH16244 16-bit Buffers / Drivers Renesas
HD74ALVCH16245 6-bit Bus Transceivers Renesas
HD74ALVCH162501 18-bit Universal Bus Transceivers Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74ALVCH162244 16-bit Buffers / Drivers with 3-state Outputs
HD74ALVCH162270 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
HD74ALVCH162334 16-bit Universal Bus Driver with 3-state Outputs
HD74ALVCH162373 16-bit Transparent D-type Latches with 3-state Outputs
HD74ALVCH162374 16-bit Edge triggered D-type Flip Flops with 3-state Outputs

Full PDF Text Transcription

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HD74ALVCH162260 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs ADE-205-177B (Z) 3rd. Edition December 1999 Description The HD74ALVCH162260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and / or demultiplexing of address and data information in microprocessor or bus interface applications. This device is also useful in memory interleaving applications. Three 12-bit I / O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and / or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions.
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