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HD74ALVCH162244 - 16-bit Buffers / Drivers with 3-state Outputs

Description

The HD74ALVCH162244 is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

Features

  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • High output current ±12 mA (@VCC = 3.0 V).
  • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors.
  • All outputs have equivalent 26 Ω series resistors, so no external resistors are required. HD74ALVCH162244 Function Table Inputs OE L L H H : High level L : Low level X : Imma.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74ALVCH162244 16-bit Buffers / Drivers Renesas
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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74ALVCH162260 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
HD74ALVCH162270 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
HD74ALVCH162334 16-bit Universal Bus Driver with 3-state Outputs
HD74ALVCH162373 16-bit Transparent D-type Latches with 3-state Outputs
HD74ALVCH162374 16-bit Edge triggered D-type Flip Flops with 3-state Outputs

Full PDF Text Transcription

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HD74ALVCH162244 16-bit Buffers / Drivers with 3-state Outputs ADE-205-173A (Z) Preliminary 2nd. Edition January 1998 Description The HD74ALVCH162244 is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable ( OE) inputs. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
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