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HD74ALVCH16269 - 12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs

Description

The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port.

The device is particularly suitable as an interface between synchronous DRAMs and high speed microprocessors.

Features

  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • High output current ±24 mA (@VCC = 3.0 V).
  • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors HD74ALVCH16269 Function Table Inputs CLK ↑ ↑ ↑ ↑ OEA H H L L OEB H L H L Outputs A Z Z Active Active 1B, 2B Z Active Z Active Output enable Inputs CLKENA1 H L L X X CLKENA2 H X X L L.

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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74ALVCH16260 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
HD74ALVCH162244 16-bit Buffers / Drivers with 3-state Outputs
HD74ALVCH162260 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
HD74ALVCH162270 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
HD74ALVCH162334 16-bit Universal Bus Driver with 3-state Outputs

Full PDF Text Transcription

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HD74ALVCH16269 12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs ADE-205-136 (Z) Preliminary 1st. Edition May 1996 Description The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high speed microprocessors. Data is stored in the internal B port registers on the low to high transition of the clock (CLK) input when the appropriate clock enable (CLKENA ) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B to A direction, a single storage register is provided.
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